--
-- Copyright 2006 Mentor Graphics Corporation
--
-- All Rights Reserved.
--
-- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
-- MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
--
entity counter is
port (count : buffer bit_vector(8 downto 1);
clk : in bit;
reset : in bit);
end;
architecture only of counter is
constant tpd_reset_to_count : time := 3 ns;
constant tpd_clk_to_count : time := 2 ns;
function increment(val : bit_vector) return bit_vector
is
-- normalize the indexing
alias input : bit_vector(val'length downto 1) is val;
variable result : bit_vector(input'range) := input;
variable carry : bit := '1';
begin
for i in input'low to input'high loop
result(i) := input(i) xor carry;
carry := input(i) and carry;
exit when carry = '0';
end loop;
return result;
end increment;
begin
ctr:
process(clk, reset)
begin
if (reset = '1') then
if reset'event then
count <= (others => '0') after tpd_reset_to_count;
end if;
elsif clk'event and (clk = '1') then
count <= increment(count) after tpd_clk_to_count;
end if;
end process;
end only;
--
-- Copyright 2006 Mentor Graphics Corporation
--
-- All Rights Reserved.
--
-- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
-- MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
--
entity test_counter is
PORT ( count : BUFFER bit_vector(8 downto 1));
end;
architecture only of test_counter is
COMPONENT counter
PORT ( count : BUFFER bit_vector(8 downto 1);
clk : IN bit;
reset : IN bit);
END COMPONENT ;
SIGNAL clk : bit := '0';
SIGNAL reset : bit := '0';
begin
dut : counter
PORT MAP (
count => count,
clk => clk,
reset => reset );
clock : PROCESS
begin
wait for 10 ns; clk <= not clk;
end PROCESS clock;
stimulus : PROCESS
begin
wait for 5 ns; reset <= '1';
wait for 4 ns; reset <= '0';
wait;
end PROCESS stimulus;
end only;
part6.vhd
5. D-Latch
6. D-FF, JK-FF
| 8. Memory Blocks | SRAM |
| 9. Adders, Subtractors, Multipliers |
10. PROJECT 2. DELIVER BY NOVEMBER 10, 2006
11. Timing Considerations, Finite State Machine