| Source code for DEC_7Seg.vhdl
Source code multiplexer.vhd Pin assignement file for UP-2 board NEW CHANGE IN REQUIREMENTS! September 29 1. Demonstrate all projects-tutorials using:
performed so far. This does not include HOME PROJECT_1. 2. Demonstrate knowledge in programming FPGA device on the UP-2 board. YOU will be graded!! October 04 3. October 04, 2006 5:00pm Room NAC 5-102 QUIZ on the CSC342 all topics that we have discussed in the class (including chapt. 3.0, 3.1, 3.2, Appendix B, and Ch. 1 from the Comput. Org. book). October 06 lab Download working Home Project _1 SOLUTION for QUARTUS and MODELSIM. You have to simulate ( YyOU DO NOT NEED TO COMPILE) and analyze waveforms in both cases and demonstrate in the lab on October 06. YOU Will be graded! October 13 Create a reduced version of the working project that fits on the UP-2 board. You may create your own design. REPORTING:
1. Design and verify your design in simulation using MODEL_SIM . The waveforms obtained using MODEL-SIM should correspond to the waveforms given in the specification., 2. Created a project in QUARTUS using the same design and test VHDL files you have created in MODEL_SIM. Complie and simulate your design again. 3. Create and NET-List for the FPGA device on UP-2 board. 4. Verify your design on the board. The result you obtain on the board should correspond to specification and your simulation. Please have fun and enjoy your project! SUMMARY : |
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