Block instance name AltBus10Bit
Block type altbus
Simulation sampling period value     0 ns
Port Section
1      Input Port
1    Output Port
O1 is driving a bus [10].[0]



Block instance name BitAltBus5_10bit
Block type altbus
Simulation sampling period value     0 ns
Port Section
1      Input Port
1    Output Port
O1 is driving a bus [10].[0]



Block instance name AltBus1
Block type altbus
Simulation sampling period value     0 ns
Port Section
1    Output Port
O1 is driving a bus [8].[0]



Block instance name AltBus2
Block type altbus
Simulation sampling period value     0 ns
Port Section
1    Output Port
O1 is driving a bus [10].[0]



Block instance name AltBus3
Block type altbus
Simulation sampling period value     0 ns
Port Section
1    Output Port
O1 is driving a bus [10].[0]



Block instance name AltBus6
Block type altbus
Simulation sampling period value     0 ns
Port Section
1    Output Port
O1 is driving a bus [8].[0]



Block instance name AltBus7
Block type altbus
Simulation sampling period value     0 ns
Port Section
1    Output Port
O1 is driving a bus [10].[0]



Block instance name AltBus8
Block type altbus
Simulation sampling period value     0 ns
Port Section
1    Output Port
O1 is driving a bus [10].[0]



Block instance name Constant1_10_Bit_signed
Block type altbus
Simulation sampling period value     0 ns
Port Section
1    Output Port
O1 is driving a bus [10].[0]



Block instance name Constant_10_Bit_signed
Block type altbus
Simulation sampling period value     0 ns
Port Section
1    Output Port
O1 is driving a bus [10].[0]



Block instance name SelectPower24BitSELECT
Block type altbus
Simulation sampling period value     0 ns
Port Section
1      Input Port
1    Output Port
O1 is driving a bus [5].[0]



Block instance name UnsgnInt4BitSELECT
Block type altbus
Simulation sampling period value     0 ns
Port Section
1      Input Port
1    Output Port
O1 is driving a bus [5].[0]



Block instance name nto1MultiplexerFullBinary
Block type multiplebusmux
Simulation sampling period value     0 ns
Port Section
5      Input Port
I1 is driven by a bus [5].[0]
I2 is driven by a bus [8].[0]
I3 is driven by a bus [10].[0]
I4 is driven by a bus [10].[0]
I5 is driven by a bus [10].[0]
1    Output Port
O1 is driving a bus [10].[0]



Block instance name nto1MultiplexerOneHot
Block type multiplebusmux
Simulation sampling period value     0 ns
Port Section
5      Input Port
I1 is driven by a bus [5].[0]
I2 is driven by a bus [8].[0]
I3 is driven by a bus [10].[0]
I4 is driven by a bus [10].[0]
I5 is driven by a bus [10].[0]
1    Output Port
O1 is driving a bus [10].[0]



Block instance name BusBuild
Block type buildbus
Simulation sampling period value     0 ns
Port Section
4      Input Port
I1 is driven by a bus [1].[0]
I2 is driven by a bus [1].[0]
I3 is driven by a bus [1].[0]
I4 is driven by a bus [1].[0]
1    Output Port
O1 is driving a bus [5].[0]



Block instance name Pattern
Block type synchronizer
Simulation sampling period value     0 ns
Port Section
1    Output Port
O1 is driving a bus [1].[0]



Block instance name Pattern1
Block type synchronizer
Simulation sampling period value     0 ns
Port Section
1    Output Port
O1 is driving a bus [1].[0]



Block instance name Pattern2
Block type synchronizer
Simulation sampling period value     0 ns
Port Section
1    Output Port
O1 is driving a bus [1].[0]



Block instance name Pattern3
Block type synchronizer
Simulation sampling period value     0 ns
Port Section
1    Output Port
O1 is driving a bus [1].[0]



Block instance name IncrementDecrement
Block type hdlentity
Simulation sampling period value     0 ns
Port Section
1    Output Port
O1 is driving a bus [5].[0]


The Block Information Table provides bit width information for input and output ports of the DSP Builder blocks used in the design muxDemo

Bit width information

.mdl . The following notation is used:

         Simulink Block Name (VHDL Instance Name) :
                 i(Input port number) [L].[R]
                 o(Output port number) [L].[R]

[L] is the number of bit on the left side of the binary point. [R] is the number of bit on the right side of the binary point. [L].[R] Simulink signal is mapped to the signal type std_logic_vector(L+R-1 downto 0) from VHDL library package ieee.std_logic_1164.all. [R]=0 when the bus type is Signed Integer or Unsigned Integer. The most significant bit of the bus is the sign bit when the bus type is Signed Integer or Signed Binary Fractional

Simulation sampling period value

The Simulation sampling period value is the value that Simulink uses to simulate the block.In order to maintain cycle accuracy between Simulink and HDL simulation, it's important to verify that the clock domains of the hardware design matches the sampling frequencyFor Designs using the altera PLL block, the Simulation sampling period value should match the PLL output value.For Designs which are not using PLL blocks, each Simulation sampling period value of all blocks should be equal to the clock value used in hardware.

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