SignalCompiler report

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Project Setting

Model muxDemo
Directory C:\CS342Fall2006\MUX
Device family STRATIX
Synthesis tool   Quartus II
Optimization Speed
Date Tuesday, August 29, 2006
Time 15:24:14
Version 6.0 Build 202

Compilation status

Convert Mdl to VHDL   :    PASSED    
Synthesis    :    PASSED    muxDemo.map.rpt
Quartus II Fitter :    PASSED     muxDemo.fit.rpt
Timing Analyzer report :muxDemo.fit.tan

Resource Usage Summary

ResourceUsage
Total logic elements17
-- Combinational with no register7
-- Register only0
-- Combinational with a register10
Logic element usage by number of LUT inputs
-- 4 input functions6
-- 3 input functions6
-- 2 input functions5
-- 1 input functions0
-- 0 input functions0
-- Combinational cells for routing0
Logic elements by mode
-- normal mode17
-- arithmetic mode0
-- qfbk mode0
-- register cascade mode0
-- synchronous clear/load mode0
-- asynchronous clear/load mode0
Total registers10
I/O pins30
Maximum fan-out nodesclrp
Maximum fan-out10
Total fan-out85
Average fan-out1.81

Fitter StatusSuccessful - Tue Aug 29 15:25:16 2006 ResourceUsage Total logic elements18 / 10,570 ( < 1 % ) -- Combinational with no register8 -- Register only0 -- Combinational with a register10 Logic element usage by number of LUT inputs -- 4 input functions6 -- 3 input functions6 -- 2 input functions5 -- 1 input functions0 -- 0 input functions1 Logic elements by mode -- normal mode18 -- arithmetic mode0 -- qfbk mode0 -- register cascade mode0 -- synchronous clear/load mode0 -- asynchronous clear/load mode0 Total LABs3 / 1,057 ( < 1 % ) Logic elements in carry chains0 User inserted logic elements 0 Virtual pins0 I/O pins30 / 336 ( 9 % ) -- Clock pins 1 / 16 ( 6 % ) Global signals 1 M512s0 / 94 ( 0 % ) M4Ks0 / 60 ( 0 % ) M-RAMs0 / 1 ( 0 % ) Total memory bits0 / 920,448 ( 0 % ) Total RAM block bits0 / 920,448 ( 0 % ) DSP block 9-bit elements0 / 48 ( 0 % ) PLLs0 / 6 ( 0 % ) Global clocks1 / 16 ( 6 % ) Regional clocks0 / 16 ( 0 % ) Fast regional clocks0 / 8 ( 0 % ) SERDES transmitters0 / 44 ( 0 % ) SERDES receivers0 / 44 ( 0 % ) Maximum fan-out nodesclrp Maximum fan-out10 Highest non-global fan-out signalsclrp Highest non-global fan-out10 Total fan-out90 Average fan-out1.84

Resource Utilization

Analysis & Synthesis StatusSuccessful - Tue Aug 29 15:24:41 2006
Quartus II Version6.0 Build 178 04/27/2006 SJ Full Version
Revision NamemuxDemo
Top-level Entity NamemuxDemo
FamilyStratix
Total logic elements17
Total pins30
Total virtual pins0
Total memory bits0
DSP block 9-bit elements0
Total PLLs0
Total DLLs0

Pin-Out

Pin name                       Pin Direction            Bus Type           
clock in std_logic
sclrp in std_logic
AltBus10Bit out std_logic_vector(9 downto 0)
BitAltBus5_10bit out std_logic_vector(9 downto 0)
SelectPower24BitSELECT out std_logic_vector(3 downto 0)
UnsgnInt4BitSELECT out std_logic_vector(3 downto 0) )

Clock input pin (clock):   All registered blocks use the input clock signal 'clock'. muxDemo.mdl does not use PLL.
Reset input pin (sclrp):   All registered blocks use the global reset input signal 'sclrp' , which is synchronous and active high


Files generated by SignalCompiler

muxDemo.vhd   VHDL representation of the design for synthesis and simulation
muxDemo_quartus.tcl   Tcl script for Quartus® II compilation.

When compiling the design manually in the Quartus II software, type source muxDemo_quartus.tcl in the Quartus II tcl console (Auxiliary Windows). The Quartus II software executes the Tcl script that sets up the project and environment for your design.

muxDemo.vec   Quartus® II simulation vector file
muxDemo.bsf   Quartus® II symbol file
tb_muxDemo.vhd   VHDL design testbench for simulation
tb_muxDemo.tcl   Tcl script for ModelSim simulation

type do tb_muxDemo.tcl at Modelsim prompt.

tb_muxDemo.v   Verilog design testbench for simulation with Quartus II Verilog Output File (.vo)


Synthesis & compilation log files

Quartus II Map Log

Quartus II Fit Log


Entity muxDemo

Information page on the DSP Builder blocks used in muxDemo.

Bus width extension

In order to maintain bit accuracy between the Simulink domain and the VHDL domain, the MDL to VHDL conversion process may extend or reduce bus width. This occurs
- When the block input port bit width is greater than the signal input port bit width, SignalCompiler sign extends the signal bit width to the input port bit width.
- When the block input port bit width is smaller than the signal input port bit width, SignalCompiler truncates the signal bit width to the input port bit width.
- For designs in which unsigned integer signals are used in Simulink, SignalCompiler translates the Simulink unsigned bus type with width w into a VHDL signed bus of width w + 1 where the MSB bit is stuck to 0.

	"nto1MultiplexerFullBinary" : input port "datasub13_0Mux" [10].[0] is driven by a signal [8].[0].
	"nto1MultiplexerFullBinary" : input port "Sel_13_Mux" [2].[0] is driven by a signal [5].[0].
	"nto1MultiplexerOneHot" : input port "datasub14_0Mux" [10].[0] is driven by a signal [8].[0].
	"nto1MultiplexerOneHot" : input port "Sel_14_Mux" [4].[0] is driven by a signal [5].[0].

Warning Section


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DSP Builder
Quartus II development tool and MATLAB/Simulink Interface
Version 6.0 Build 202

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