SignalCompiler report
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Project Setting
Model | muxDemo |
Directory | C:\CS342Fall2006\MUX |
Device family | STRATIX |
Synthesis tool | Quartus II |
Optimization | Speed |
Date | Tuesday, August 29, 2006 |
Time | 15:24:14 |
Version | 6.0 Build 202 |
Compilation status
Resource Usage Summary
Resource | Usage |
Total logic elements | 17 |
-- Combinational with no register | 7 |
-- Register only | 0 |
-- Combinational with a register | 10 |
| |
Logic element usage by number of LUT inputs | |
-- 4 input functions | 6 |
-- 3 input functions | 6 |
-- 2 input functions | 5 |
-- 1 input functions | 0 |
-- 0 input functions | 0 |
-- Combinational cells for routing | 0 |
| |
Logic elements by mode | |
-- normal mode | 17 |
-- arithmetic mode | 0 |
-- qfbk mode | 0 |
-- register cascade mode | 0 |
-- synchronous clear/load mode | 0 |
-- asynchronous clear/load mode | 0 |
| |
Total registers | 10 |
I/O pins | 30 |
Maximum fan-out node | sclrp |
Maximum fan-out | 10 |
Total fan-out | 85 |
Average fan-out | 1.81 |
Fitter Status | Successful - Tue Aug 29 15:25:16 2006 |
Resource | Usage |
Total logic elements | 18 / 10,570 ( < 1 % ) |
-- Combinational with no register | 8 |
-- Register only | 0 |
-- Combinational with a register | 10 |
| |
Logic element usage by number of LUT inputs | |
-- 4 input functions | 6 |
-- 3 input functions | 6 |
-- 2 input functions | 5 |
-- 1 input functions | 0 |
-- 0 input functions | 1 |
| |
Logic elements by mode | |
-- normal mode | 18 |
-- arithmetic mode | 0 |
-- qfbk mode | 0 |
-- register cascade mode | 0 |
-- synchronous clear/load mode | 0 |
-- asynchronous clear/load mode | 0 |
| |
Total LABs | 3 / 1,057 ( < 1 % ) |
Logic elements in carry chains | 0 |
User inserted logic elements | 0 |
Virtual pins | 0 |
I/O pins | 30 / 336 ( 9 % ) |
-- Clock pins | 1 / 16 ( 6 % ) |
Global signals | 1 |
M512s | 0 / 94 ( 0 % ) |
M4Ks | 0 / 60 ( 0 % ) |
M-RAMs | 0 / 1 ( 0 % ) |
Total memory bits | 0 / 920,448 ( 0 % ) |
Total RAM block bits | 0 / 920,448 ( 0 % ) |
DSP block 9-bit elements | 0 / 48 ( 0 % ) |
PLLs | 0 / 6 ( 0 % ) |
Global clocks | 1 / 16 ( 6 % ) |
Regional clocks | 0 / 16 ( 0 % ) |
Fast regional clocks | 0 / 8 ( 0 % ) |
SERDES transmitters | 0 / 44 ( 0 % ) |
SERDES receivers | 0 / 44 ( 0 % ) |
Maximum fan-out node | sclrp |
Maximum fan-out | 10 |
Highest non-global fan-out signal | sclrp |
Highest non-global fan-out | 10 |
Total fan-out | 90 |
Average fan-out | 1.84 |
Resource Utilization
Analysis & Synthesis Status | Successful - Tue Aug 29 15:24:41 2006 |
Quartus II Version | 6.0 Build 178 04/27/2006 SJ Full Version |
Revision Name | muxDemo |
Top-level Entity Name | muxDemo |
Family | Stratix |
Total logic elements | 17 |
Total pins | 30 |
Total virtual pins | 0 |
Total memory bits | 0 |
DSP block 9-bit elements | 0 |
Total PLLs | 0 |
Total DLLs | 0 |
Pin-Out
Pin name |
Pin Direction |
Bus Type |
clock | in | std_logic |
sclrp | in | std_logic |
AltBus10Bit | out | std_logic_vector(9 downto 0) |
BitAltBus5_10bit | out | std_logic_vector(9 downto 0) |
SelectPower24BitSELECT | out | std_logic_vector(3 downto 0) |
UnsgnInt4BitSELECT | out | std_logic_vector(3 downto 0) ) |
|
Clock input pin (clock):
All registered blocks use the input clock signal 'clock'. muxDemo.mdl does not use PLL.
Reset input pin (sclrp):
All registered blocks use the global reset input signal 'sclrp' , which is synchronous and active high
Files generated by SignalCompiler
muxDemo.vhd | VHDL representation of the design for synthesis and simulation |
muxDemo_quartus.tcl | Tcl script for Quartus® II compilation. When compiling the design manually in the Quartus II software, type source muxDemo_quartus.tcl in the Quartus II tcl console (Auxiliary Windows). The Quartus II software executes the Tcl script that sets up the project and environment for your design. |
muxDemo.vec | Quartus® II simulation vector file |
muxDemo.bsf | Quartus® II symbol file |
tb_muxDemo.vhd | VHDL design testbench for simulation |
tb_muxDemo.tcl | Tcl script for ModelSim simulation type do tb_muxDemo.tcl at Modelsim prompt. |
tb_muxDemo.v | Verilog design testbench for simulation with Quartus II Verilog Output File (.vo) |
Synthesis & compilation log files
Quartus II Map Log
Quartus II Fit Log
Entity muxDemo
Information page on the DSP Builder blocks used in muxDemo.
Bus width extension
In order to maintain bit accuracy between the Simulink domain and the VHDL domain, the MDL to VHDL conversion process may extend or reduce bus width. This occurs
- When the block input port bit width is greater than the signal input port bit width, SignalCompiler sign extends the signal bit width to the input port bit width. |
- When the block input port bit width is smaller than the signal input port bit width, SignalCompiler truncates the signal bit width to the input port bit width. |
- For designs in which unsigned integer signals are used in Simulink, SignalCompiler translates the Simulink unsigned bus type with width w into a VHDL signed bus of width w + 1 where the MSB bit is stuck to 0. |
"nto1MultiplexerFullBinary" : input port "datasub13_0Mux" [10].[0] is driven by a signal [8].[0].
"nto1MultiplexerFullBinary" : input port "Sel_13_Mux" [2].[0] is driven by a signal [5].[0].
"nto1MultiplexerOneHot" : input port "datasub14_0Mux" [10].[0] is driven by a signal [8].[0].
"nto1MultiplexerOneHot" : input port "Sel_14_Mux" [4].[0] is driven by a signal [5].[0].
Warning Section
DSP Builder
Quartus II development tool and MATLAB/Simulink Interface
Version 6.0 Build 202 Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
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Please refer to the applicable agreement for further details.