CS 342 Computer Organization and Design
Fall 2010
Catalog
Description
This course provides computer
science and computer engineering students with an in-depth look at computer
architecture and the hardware/software interface. The major topics are: computer
abstractions and technology; the role of performance and measuring performance;
SPEC. computer arithmetic; machine language: a comparative analysis of
instruction sets of current processors using the debuggers, simulators and by
the partial reverse engineering of executables. The processor: datapath and
control; RISC versus CISC; design, implementation (using VHDL), and
verification (in simulation) of a simplified RISC processor using CAD tools.
Enhancing performance with pipelining. Memory hierarchy, cache, virtual memory,
performance issues. Interfacing processors and peripherals; PCI chipset.
Overview of multiprocessors, grid computing.
Organization
and Schedule Lecture 3, Credit 3, Laboratory (CS 343) 3, Credit 1
Semester Meeting
Type Days Time Location Dates
Fall 2010 Lecture
M,W
5:00
– 6:15 PM NAC 5-109 Aug.
28 – Dec. 16
Fall 2010 Laboratory
Friday 10:15–
1:15 PM NAC 5-103 Aug.
28 – Dec. 16
Prerequisites Required: Cs210.
Corequisites CS
343
Course
Goals
This course teaches you interaction between
hardware and software at a variety of levels. The emphasis in this course is to show relashionship between
hardware and software and to analyze the concepts that are basis for current
computers.
Course Audience
This is a core course for Computer Science and Computer Engineering majors. The students are expected to have little experience in assembly language and logic design.
Technology and
Tools Used In This Course
·
Microsoft
Windows XP, Vista (operating
system used in the laboratory)
·
LINUX
(operating system used in the laboratory)
·
Microsoft
Visual Studio(C++ compiler, linker, assembler)
·
Microsoft
Visual Studio (debugger)
·
Gnu
C++ compiler (gcc) on LINUX
·
SPIM
–MIPS instruction set simulator
·
Intel®
Streaming SIMD Extensions (SSE) (
for accelerating vector operations)
·
OPTIONAL:
NVIDIA® CUDA™ parallel compute engine in NVIDIA
graphics processing units (GPUs) (for parallel computing)
Course
Coordinator
Name Office Phone Email
Address Office
Hours
Izidor Gertner
NAC 8-202F 212-650-6173 csicg@cs.ccny.cuny.edu M,W
4:00-5:00 PM
Required Textbook
David Patterson
and John Hennessy , Computer
Organization and Design, Fourth Edition: The Hardware/Software Interface,
Morgan-Kaufman, 2009.
Recommended References
Intel, Microsoft, Altera, NVIDIA documentation and papers available on
their websites.
Major Topics Covered in the
Course
2. The Role of Performance and Measuring Performance, SPEC Benchmarks and Performance of Recent Processors( 1 hour)
3. Computer Arithmetic( 3 hours)
4. Machine Language: Comparative study of Pentium, MIPS instruction sets using debuggers, simulators and by partial reverse engineering of executables. (6 hours)
5. The Processor: Datapath and Control; RISC versus CISC; Design, implementation( using VHDL) , and verification( in simulation) of simplified RISC processor using software tools from ALTERA Corp. (6 hours)
6. Enhancing performance with pipelining, SSE –Streaming SIMD Extension (4 hours)
7. Memory Hierarchy, Cache, Virtual Memory, Performance issues.( 3 hours)
8. Interfacing Processors and Peripherals; PCI Chipset. (2 hours)
9. Overview of multiprocessors, GPU computing (2hours)
10. Tests.(3 hours)
Grading Policy:
1. micro-Quiz: 5%
2. Quiz 1: 15%
3. Quiz 2a: 10%
4. Quiz 2b: 10%
5. Quiz 3: 10%
6. Final Quiz: 25%
7. Home Assignments:
Programming, Exercises 25%
The Programming assignments and exercises
provide essential material for the quizzes. The assignments will be primarily graded on an effort basis and proper
presentation. Each report should
contain the following sections:Objective, Source code, Explanations and Screen
shots, Conclusions.