Cs343 Course Description

 

Dept., Number

CSc 34300

Course Title

Computer Systems Design Laboratory

Semester  hours

 

3h20 /wk

1 cr.

Course Coordinator

Prof. Izidor Gertner

 

 

Instructor

Steven Medina

 

Current Catalog Description

 

Introduction to FPLD technology, logic synthesis, and rapid prototyping of digital systems using commercial CAD tools. Topics:Programmable Logic Technology. Sequential Design and Hierarchy. Synthesis of Digital Hardware using VHDL. State Machine Design, CPU Controller. A Simple Processor Design. Video Graphics Adapter(VGA) video display generation. Design PS/2 Keyboard interface. Design of PS/2 Mouse interface. Synthesis of a RISC processor as covered in CSc 34200. Students are required to prepare written reports and demonstrate their design.

 

Textbook

 

         Furman, Michael D., Rapid Prototyping of Digital Systems, 4th edition, Publisher: Springer, 2007

 

References

 

 

http://www.altera.com

     

Course Outcomes

 

  1. Ability to use commercial computer-aided design tools ModelSim, Quartus to design, simulate, and to perform functional and timing verification of digital circuits.
  2. Ability to use and to program Field Programmable Gate Array ( FPGA) devices.
  3. Basic Knowledge of VHDL and use of Megacore libraries.

4.     Ability to prepare, present and defend a report that demonstrates correct implementation of the design on a FPGA device.

 

                      

Relationship between Course Outcomes and Program Outcomes

Course Outcome (by number)

Program Outcome (by letter)

1

a, b, c, i, j

2

b, c, i

3

a, b, c, i, j, k

4

d, f

 

 

                      

Prerequisites by Topic

 

Co-requisite: CSc 34200.

 

Major Topics Covered in the Course

 

Laboratory Projects

Students design, simulate and verify the correctness of digital circuits using ModelSim and Quatrus CAD tools.  Students have to test their designs on a FPGA device and prepare a demo and a report.

Specific projects:

1. Adders: These adders include half-adders, full-adders

        1.1 Then students design an Overflow Detection circuit

2. Memory Elements design: The purpose of this lab is to investigate Latches, Flip-Flops, and

    Registers and their timing.

3. Finite State Machine design: The purpose of this lab is implement a FSM that recognizes two

    specific sequences at the input.

4. Clocks and Timers: implement 3-digit BCD counter using real-time clock.

5  Multipliers: Design a circuit to implement multiplication algorithm

6. Memory: use as megacore memory block to store and retrieve values.

7. Simple Processor: In this lab, the students design a simple processor. This processor must

    execute four instructions: move, move-immediate, add, and subtract.

 

Assessment Plan for the Course

 

 Students are required to prepare written reports and demonstrate their design.

 

 

                                How Data in the Course is Used to Assess Program Outcomes (unless adequately covered already in the assessment discussion under Criterion 4)

 

covered already in the assessment discussion

 

For a computer science program 

Estimate Curriculum Category Content (Semester hours)

 

Area

Core

Advanced

Area

Core

Advanced

Algorithms

 

 

Software design

 

 

Data structures

 

 

Concepts of programming languages

 

 

Computer organization and architecture